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19-2921; Rev 1; 12/03
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range
General Description
The MAX1272/MAX1273 multirange 12-bit data-acquisition systems (DAS) operate with a single 5V supply. The software-programmable analog input accepts a variety of voltage ranges: 10V, 5V, 0 to 10V, 0 to 5V for the MAX1272; VREF, VREF / 2, 0 to VREF, 0 to VREF / 2 for the MAX1273. The software-selectable extended analog input range increases the effective dynamic range to 14 bits and provides the flexibility to interface 4-20mA powered sensors directly to a single 5V system. In addition, the MAX1272 provides fault protection to 12V. Other features include a 5MHz track/hold (T/H) bandwidth, 87ksps throughput rate, and internal (4.096V) or external (2.40V to 4.18V) reference. The MAX1272/MAX1273 serial interfaces connect directly to SPITM/QSPITM/MICROWIRETM-compatible devices without any external logic. Four software-programmable power-down modes (delayed standby, immediate standby, delayed full powerdown, and immediate full power-down) provide low-current shutdown between conversions. In standby mode, the internal reference buffer remains active, thus eliminating startup delay. The MAX1272/MAX1273 are available in 8-pin PDIP and MAX packages. Both devices are available in the commercial (0C to +70C) or extended (-40C to +85C) temperature range.
Features
o Four Software-Selectable Input Ranges MAX1272: 0 to 10V, 0 to 5V, 10V, 5V MAX1273: 0 to VREF, 0 to VREF / 2, VREF, VREF / 2 o 12-Bit Resolution, No Missing Codes o 5V Single-Supply Operation o SPI/QSPI/MICROWIRE-Compatible 3-Wire Interface o 87ksps Sampling Rate o 12V Fault-Protected Analog Input (MAX1272) o Internal (4.096V) or External (2.4V to 4.18V) Reference o Low Power 1.5mA at 87ksps 0.4mA at 10ksps 0.2mA at 1ksps o Four Power-Down Modes o 8-Pin MAX and PDIP Packages
MAX1272/MAX1273
Ordering Information
PART MAX1272CPA MAX1272CUA MAX1272EPA MAX1272EUA MAX1273CPA MAX1273CUA MAX1273EPA MAX1273EUA TEMP RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0C to +70C 0C to +70C -40C to +85C -40C to +85C PINPACKAGE 8 Plastic DIP 8 MAX 8 Plastic DIP 8 MAX 8 Plastic DIP 8 MAX 8 Plastic DIP 8 MAX INL (LSB) 1 1 1 1 1 1 1 1
Applications
Industrial Control Systems Data-Acquisition Systems Robotics Automatic Testing Battery-Powered Instruments Medical Instruments
Pin Configuration
TOP VIEW
SCLK DIN 1 2 3 8 7 DOUT CS REF AIN
Typical Application Circuit appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
VDD
MAX1272 MAX1273
6 5
GND 4
PDIP/MAX
________________________________________________________________ Maxim Integrated Products
1
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V AIN to GND (MAX1272) ...................................................... 12V AIN to GND (MAX1273) ........................................................ 6V DOUT, CS, DIN, SCLK, REF to GND..........-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.1mW/C above +70C) ......727mW 8-Pin MAX (derate 4.5mW/C above +70C) ..............362mW Operating Temperature Ranges MAX127_ C_ _ .....................................................0C to +70C MAX127_ E_ _...................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C Junction Temperature .....................................................+150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, VREF = 4.096V, CREF = 1.0F, fSCLK = 1.4MHz, 50% duty cycle, CLOAD = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETERS ACCURACY (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error (Note 2) Gain Error Temperature Coefficient (Note 2) Signal-to-Noise + Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Aperture Delay Aperture Jitter ANALOG INPUT T/H Acquisition Time tACQ 2.85 s SINAD THD SFDR tAD tAJ Up to the 5th harmonic 80 INL DNL No missing codes over temperature Unipolar Bipolar Unipolar Bipolar Unipolar Bipolar 69 3 5 72 -87 88 15 <50 -78 SYMBOL CONDITIONS MIN 12 0.3 0.35 1.0 1.00 5 10 10 10 LSB ppm/C TYP MAX UNITS Bits LSB LSB LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 10VP-P (MAX1272), or 4.096VP-P (MAX1273), fSAMPLE = 87ksps) dB dB dB ns ps
2
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, VREF = 4.096V, CREF = 1.0F, fSCLK = 1.4MHz, 50% duty cycle, CLOAD = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETERS SYMBOL CONDITIONS 10V (MAX1272) or VREF (MAX1273) range 5V (MAX1272) or VREF / 2 (MAX1273) range Small-Signal Bandwidth BW-3dB 0 to 10V (MAX1272) or 0 to VREF (MAX1273) range 0 to 5V (MAX1272) or 0 to VREF / 2 (MAX1273) range MAX1272 Unipolar MAX1273 Input Voltage Range (Tables 2, 3) VIN MAX1272 Bipolar MAX1273 MAX1272 Unipolar MAX1273 Input Current IIN MAX1272 Bipolar MAX1273 Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Output Tempco Output Short-Circuit Current Load Regulation Capacitive Bypass at REF REFERENCE INPUT (Reference buffer disabled, reference input applied to REF) Input Voltage Range VREF TC VREF MAX127_ C MAX127_ E REF shorted to GND 0 to 0.5mA output current 1 2.40 4.18 4.036 4.096 15 30 40 0.7 10 4.156 V ppm/C mA mV F V RNG = 1 RNG = 0 RNG = 1 RNG = 0 RNG = 1 RNG = 0 RNG = 1 RNG = 0 0 to 10V range 0 to 5V range 0 to VREF range 0 to VREF / 2 range 10V range 5V range VREF range VREF / 2 range 0 0 0 0 -10 -5 -VREF -VREF / 2 -10 -10 -10 -10 -1400 -720 -1400 -720 40 MIN TYP 5 2.5 MHz 2.5 1.25 10 5 VREF VREF / 2 +10 +5 +VREF +VREF / 2 +860 +430 +10 +10 +860 +430 +10 +10 pF A V MAX UNITS
MAX1272/MAX1273
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, VREF = 4.096V, CREF = 1.0F, fSCLK = 1.4MHz, 50% duty cycle, CLOAD = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETERS SYMBOL CONDITIONS Converting VREF = 4.096V Standby power-down mode Full power-down mode POWER REQUIREMENTS Supply Voltage Supply Current (Internal Reference Mode) VDD Converting IDD Bipolar Unipolar 4.75 5 2.4 2.2 400 1 1.5 1.2 200 1 0.3 0.5 0.1 (Note 4) (Note 4) REF bypass capacitor initially discharged External reference mode VIH VIL VHYS IIN CIN ISINK = 10mA ISINK = 16mA ISOURCE = 0.5mA CS = VDD CS = VDD VDD - 0.5 -10 15 +10 0.6 VIN = 0 to VDD -10 15 0.4 0.8 0.2 +10 2.85 8.57 87.5 2 10 2.4 1.4 1.0 2.5 2.0 450 MIN TYP 400 5 MAX 850 10 1 5.25 4 3 700 V mA A mA A LSB UNITS
Input Current
A
Standby power-down mode Full power-down mode Converting Bipolar Unipolar
Supply Current (External Reference Mode)
IDD
Standby power-down mode Full power-down mode External reference = 4.096V Internal reference
Power-Supply Rejection Ratio (Note 3) TIMING Clock Frequency Range T/H Acquisition Time Conversion Time Throughput Rate Internal Reference Settling Time Device Power-Up Time
PSRR
fSCLK tACQ tCONV
MHz s s ksps ms s V V V A pF
DIGITAL INPUTS (DIN, SCLK, and CS) Input High-Threshold Voltage Input Low-Threshold Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (DOUT) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VOL VOH IL COUT V V A pF
4
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range
TIMING CHARACTERISTICS
(VDD = 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, VREF = 4.096V, CREF = 1.0F, fSCLK = 1.4MHz, 50% duty cycle, CLOAD = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Figures 1 and 4)
PARAMETERS DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SYMBOL tDS tDH tDO tDV tTR tCSS tCSH tCH tCL 100 0 200 200 20 CONDITIONS MIN 100 0 250 100 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns
MAX1272/MAX1273
Note 1: Accuracy specifications tested at VDD = 5V. Performance at power-supply tolerance limit is guaranteed by power-supply rejection test. Note 2: Offset error nulled. The ideal last-code transition is (FS - 1.5 LSB). Note 3: PSRR measured at full scale. Tested at 10V (MAX1272) and 4.096V (MAX1273) input ranges. Note 4: Acquisition and conversion times are dependent on the clock speed.
Typical Operating Characteristics
(Typical operating circuit, BIP = RNG = 1, VDD = 5V, external reference mode, VREF = 4.096V, CREF = 1.0F, fSCLK = 1.4MHz, 50% duty cycle, 87ksps, TA = +25C, unless otherwise noted.)
CONVERTING SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1272/73 toc01
CONVERTING SUPPLY CURRENT vs. TEMPERATURE
MAX1272/73 toc02
STANDBY SUPPLY CURRENT vs. TEMPERATURE
0.9 STANDBY SUPPLY CURRENT (mA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 INTERNAL REFERENCE EXTERNAL REFERENCE VAIN = 0
MAX1272/73 toc03
5.0 4.5 4.0 SUPPLY CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 EXTERNAL REFERENCE INTERNAL REFERENCE
VAIN = 0
5.0 4.5 4.0
VAIN = 0
1.0
SUPPLY CURRENT (mA)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 EXTERNAL REFERENCE INTERNAL REFERENCE
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
Typical Operating Characteristics (continued)
(Typical operating circuit, BIP = RNG = 1, VDD = 5V, external reference mode, VREF = 4.096V, CREF = 1.0F, fSCLK = 1.4MHz, 50% duty cycle, 87ksps, TA = +25C, unless otherwise noted.)
STANDBY SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1272/73 toc04
FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE
MAX1272/73 toc05
FULL POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
9 8 SUPPLY CURRENT (A) 7 6 5 4 3 2 1 0 INTERNAL/EXTERNAL REFERENCE VAIN = 0
MAX1272/73 toc06
1.0 0.9 0.8 SUPPLY CURRENT (mA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 EXTERNAL REFERENCE INTERNAL REFERENCE
VAIN = 0
10 9 8
SUPPLY CURRENT (A)
10
VAIN = 0
7 6 5 4 3 2 1 0 -40 -15 INTERNAL/EXTERNAL REFERENCE
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 SUPPLY VOLTAGE (V)
10
35
60
85
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1272/73 toc07
NORMALIZED INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
NORMALIZED INTERNAL REFERENCE VOLTAGE 1.0008 1.0006 1.0004 1.0002 1.0000 0.9998 0.9996 0.9994 0.9992 0.9990 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 SUPPLY VOLTAGE (V)
MAX1272/73 toc08
NORMALIZED INTERNAL REFERENCE VOLTAGE
1.0005 1.0000 0.9995 0.9990 0.9985 0.9980 0.9975 0.9970 0.9965 0.9960 -40 -15 10 35 60
1.0010
85
TEMPERATURE (C)
DNL vs. CODE
MAX1272/73 toc09
INL vs. CODE
0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1272/73 toc10
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0
1.0
512 1024 1536 2048 2560 3072 3584 4096 CODE
0
512 1024 1536 2048 2560 3072 3584 4096 CODE
6
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range
Typical Operating Characteristics (continued)
(Typical operating circuit, BIP = RNG = 1, VDD = 5V, external reference mode, VREF = 4.096V, CREF = 1.0F, fSCLK = 1.4MHz, 50% duty cycle, 87ksps, TA = +25C, unless otherwise noted.)
FFT PLOT
MAX1272/73 toc11
MAX1272/MAX1273
SUPPLY CURRENT vs. CONVERSION RATE
fAIN = 10kHz VAIN = 0 STANDBY POWER-DOWN MODE BETWEEN CONVERSIONS
MAX1272/73 toc12
0 -20 -40 AMPLITUDE (dB) -60 -80 -100 -120 -140 -160 0 10 20 30 40
2500
2000 SUPPLY CURRENT (A)
1500 EXTERNAL REFERENCE INTERNAL REFERENCE 500
1000
0 50 0.1 1 10 100 FREQUENCY (kHz) CONVERSION RATE (ksps)
OFFSET ERROR vs. TEMPERATURE
MAX1272/73 toc13
OFFSET ERROR vs. SUPPLY VOLTAGE
8 6 OFFSET ERROR (LSB) 4 2 0 -2 -4 -6 -8 -10 RNG = 1, BIP = 0 RNG = 0, BIP = 0 RNG = 0, BIP = 1 RNG = 1, BIP = 1
MAX1272/73 toc14
10 8 6 OFFSET ERROR (LSB) 4 2 0 -2 -4 -6 -8 -10 -40 -15 10 35 60 RNG = 1, BIP = 0 RNG = 0, BIP = 1 RNG = 0, BIP = 0 RNG = 1, BIP = 1
10
85
4.50
4.75
5.00
5.25
5.50
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
GAIN ERROR vs. TEMPERATURE
MAX1272/73 toc15
GAIN ERROR vs. SUPPLY VOLTAGE
8 6 GAIN ERROR (LSB) 4 2 0 -2 -4 -6 -8 -10 RNG = 1, BIP = 1 RNG = 1, BIP = 0 RNG = 0, BIP = 0 RNG = 0, BIP = 1
MAX1272/73 toc16
10 8 6 GAIN ERROR (LSB) 4 2 0 -2 -4 -6 -8 -10 -40 -15 10 35 60 RNG = 1, BIP = 0 RNG = 1, BIP = 1 RNG = 0, BIP = 0 RNG = 0, BIP = 1
10
85
4.50
4.75
5.00
5.25
5.50
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
Pin Description
PIN 1 2 3 4 5 6 NAME SCLK DIN VDD GND AIN REF FUNCTION Serial Clock Input. Clocks data in and out of serial interface. SCLK sets the conversion speed. Serial Data Input. Data clocks in on the rising edge of SCLK. 5V Supply. Bypass with a 0.1F capacitor to GND. Ground Analog Input Reference Buffer Output/Reference Input. Bypass REF with a 1F capacitor to GND. In internal reference mode, the reference buffer provides a 4.096V nominal output. For external reference mode, disable the internal reference buffer through the serial interface and apply an external reference to REF. Active-Low Chip-Select Input. Drive CS low to clock data into the MAX1272/MAX1273. See the Input Data Format section. Serial Data Output. Data clocks out on the falling edge of SCLK. DOUT is high impedance when CS is high.
7 8
CS DOUT
DOUT CLOAD
to convert an analog signal to a 12-bit digital output. Figure 2 shows a block diagram of the MAX1272/ MAX1273.
Analog-Input Track/Hold
1k
A) TEST CIRCUIT FOR VOH DOUT CLOAD
The T/H tracking/acquisition mode begins on the falling edge of the fourth clock cycle in the 8-bit input control word and enters hold/conversion mode on the falling edge of the eighth clock cycle. The MAX1272/MAX1273 input architecture includes a resistor-divider and a T/H system (Figure 3). When operating in bipolar or unipolar mode, the resistordivider network formed by R1, R2, and R3 scales the signal applied at the input channel. Use a low source impedance (<4) to minimize gain error.
1k
Input Bandwidth
5V
B) TEST CIRCUIT FOR VOL fSCLK = 1.4MHz, CLOAD = 50pF
Figure 1. Output Load Circuit for Timing Characteristics
Detailed Description
Converter Operation
The MAX1272/MAX1273 multirange ADCs use successive approximation and internal track/hold (T/H) circuitry
The ADC's small-signal input bandwidth depends on the selected input range and varies from 1.25MHz to 5MHz (see the Electrical Characteristics). The maximum sampling rate for the MAX1272/MAX1273 is 87ksps (16 clocks per conversion). Use undersampling techniques to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate. Use anti-alias filtering to avoid the aliasing of high-frequency signals into the frequency band of interest. An anti-aliasing filter must limit the input bandwidth to no more than one half of the sampling frequency.
8
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
DIN DOUT CS SCLK
VDD GND
SERIAL INTERFACE LOGIC
MAX1272 MAX1273
OUT 12-BIT SAR ADC REF
AIN
SIGNAL CONDITIONING
T/H
IN
CLK
REF 4.096V REFERENCE
Figure 2. Simplified Block Diagram
Table 1. Control-Byte Format
BIT 7 (MSB) START BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) BIT 6 RNG NAME START RNG BIP PD MODE1 MODE0 RESERVED REF BIT 5 BIP BIT 4 PD Bit 3 MODE1 BIT 2 MODE0 BIT 1 RESERVED BIT 0 (LSB) REF
DESCRIPTION Write a logic 1 (see the Input Data Format section) Selects the full-scale input voltage range (Tables 2, 3) Selects unipolar or bipolar conversion mode (Tables 2, 3) Selects normal operation (PD = 1) or power-down (PD = 0) mode Selects standby power-down (STBYPD) or full power-down (FULLPD) mode (Table 4) Selects delayed or immediate power-down mode (Table 4) Write a logic 0 Selects external (REF = 0, default) or internal (REF = 1) reference mode
Input Range and Protection
The MAX1272/MAX1273 provide software-selectable analog input voltage ranges. Program the analog input to one of four ranges by setting the appropriate control bits (RNG, BIP) in the control byte (Table 1). The MAX1272 has selectable input voltage ranges extending to 10V (VREF 2.4414), while the MAX1273 has selectable input voltage ranges extending to VREF. Figure 3 shows the equivalent input circuit.
Overvoltage circuitry at the analog input provides 12V fault protection for the MAX1272. This circuit limits the current going into or out of the device to less than 2mA, providing an added layer of protection from momentary over/undervoltages at the analog input. The overvoltage protection activates when the device enters powerdown mode or if VDD = 0.
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
Table 2. Input Range and Polarity Selection for MAX1272
INPUT RANGE 0 to 5V 5V 0 to 10V 10V RNG 0 0 1 1 BIP 0 1 0 1 NEGATIVE FULL SCALE -- -VREF x 1.2207 -- -VREF x 2.4414 ZERO SCALE 0 0 0 0 FULL SCALE VREF x 1.2207 VREF x 1.2207 VREF x 2.4414 VREF x 2.4414
Table 3. Input Range and Polarity Selection for MAX1273
INPUT RANGE 0 to VREF / 2 VREF / 2 0 to VREF VREF RNG 0 0 1 1 BIP 0 1 0 1 NEGATIVE FULL SCALE -- -VREF / 2 -- -VREF ZERO SCALE 0 0 0 0 FULL SCALE VREF / 2 VREF / 2 VREF VREF
Table 4. Power-Down Selection
PD 1 MODE1 X 0 0 1 MODE0 X 0 1 0 1 MODE Normal operation (ADCs always active). Automatically enters delayed standby power-down mode between conversions. Delayed standby power-down mode. Immediate standby power-down mode. Delayed full power-down mode. Immediate full power-down mode.
Input Data Format
BIPOLAR
S1
VOLTAGE REFERENCE
UNIPOLAR R3 4.8k OFF R1
CHOLD
AIN S2 ON R2 T/H OUT HOLD
S3 HOLD TRACK
TRACK
Input data (control byte) clocks in at DIN on the rising edge of SCLK. CS enables communication with the MAX1272/MAX1273. After CS falls, the first arriving 1 represents the start bit (MSB) of the input control byte. The start bit is defined as follows: 1) The first high bit clocked into DIN with CS low any time the converter is idle (e.g., after applying VDD). 2) The first high bit clocked into DIN after bit 4 (D4) of a conversion in progress clocks out on DOUT. See Table 1 for programming the control byte. Figure 4 shows the detailed serial interface timing.
S4
Output Data Format
Output data (DOUT) clocks out MSB first on the falling edge of SCLK. The unipolar mode provides a straight binary output. The bipolar mode provides a two's complement binary output. For output binary codes, see the Transfer Function section.
S1 = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH
R1 = 11.3k (MAX1272) or 4.8k (MAX1273) R2 = 7.8k (MAX1272) or (OPEN) (MAX1273)
Figure 3. Equivalent Input Circuit
10
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Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
CS
***
tCSS tCSH SCLK tDS tDH DIN tDV DOUT
tCL
tCH
tCSH
***
*** tDO *** tTR
Figure 4. Detailed Serial Interface Timing
CS
RNG
BIP
HI-Z DOUT
PD
REF
DIN
START
MODE1
MODE0
RESERVED
MSB
LSB
HI-Z
D11
D10
D7
D6
D5
D4
D3
D2
D1
D9
16
24
ACQUISITION 4 SCLKs
CONVERSION 12 SCLKs
AUTO STANDBY
Figure 5. Conversion Timing, 21 Clocks/Conversion
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32
SCLK
1
8
D8
D0
11
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
CS
CONTROL BYTE 0
CONTROL BYTE 1
CONTROL BYTE 2
RESERVED
MODE0
MODE0
RESERVED
START
MODE1
START
MODE1
RNG
RNG
RNG
REF
BIP
BIP
REF
BIP
DIN
START
PD
PD
HI-Z
MSB
RESULT 0
LSB
PD D1
MSB
RESULT 1
LSB
D10
D11
D0
D2
D1
D3
D4
D8
D5
D8
D9
D6
D9
D7
D7
D6
SCLK
ACQUISITION 4 SCLKs
CONVERSION 12 SCLKs
16
ACQUISITION 4 SCLKs
24
CONVERSION 12 SCLKs
Figure 6. Conversion Timing, 16 Clocks/Conversion
Starting a Conversion
The MAX1272/MAX1273 use the serial clock to complete an acquisition. The falling edge of CS does not start a conversion on the MAX1272/MAX1273. Each conversion requires a control byte. Programming the fourth bit in the control byte starts the acquisition sequence. Conversion starts on the falling edge of the eighth clock cycle after the start bit. Keep CS low during successive conversions. If a start bit is received after CS transitions from high to low, but before the output bit 4 (D4) becomes available, the current conversion terminates and a new conversion begins. DOUT enters high-impedance state when CS transitions high.
To achieve the maximum throughput, keep CS low, and start the control byte after bit 4 (D4) of the conversion in progress clocks out on DOUT. If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros.
Applications Information
Power-On Reset
The MAX1272/MAX1273 power-up in normal operating mode (all internal circuitry active), and external reference mode. The MAX1272/MAX1273 require a start bit to initiate a conversion. The contents of the output data register clear during power-up.
SCLK shifts data in and out of the MAX1272/MAX1273 and controls both acquisition and conversion timing. Conversion begins immediately after the end of the acquisition cycle. Successive-approximation bit decisions appear at DOUT on each of the following 12 clock falling edges (Figure 5). Additional clock falling edges result in trailing zeros at DOUT. The maximum running rate of the MAX1272/MAX1273 is 16 clocks per conversion. A clock speed of 1.4MHz allows for a maximum sampling rate of 87ksps (Figure 6).
Internal or External Reference
Operate the MAX1272/MAX1273 with an internal or an external reference. Configure REF as an internal reference output or an external reference input using the serial interface. When changing from external reference mode to internal reference mode, allow 2ms (CREF = 1F) for the reference to stabilize before taking any measurement. Internal Reference The internally trimmed reference provides 4.096V at REF. Bypass REF to GND with a 1.0F capacitor (Figure 7a).
12
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32
1
8
D5
D4
D3
D2
D0
DOUT
D11
D10
MODE1
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
5V IN
REF
MAX6064
CREF 1.0F REF OUT 1.0F CREF
MAX1272 MAX1273
MAX1272 MAX1273
GND
Figure 7a. Internal Reference Configuration
Figure 7b. External Reference Configuration
External Reference To use an external reference, disable the internal buffer by setting the REF bit in the 8-bit control word to zero (see Table 1), and apply a reference voltage to REF. Use an external reference voltage ranging from 2.40V to 4.18V. External reference voltages less than 4.096V increase the ratio of RMS noise to the LSB value (full scale / 4096) resulting in performance degradation (loss of effective bits--ENOB). The REF input impedance is a minimum of 4.8k for DC currents; therefore, the external reference must be able to source 850A during conversions and have an output impedance of less than 10. Bypass REF with a 1F capacitor to GND as close to REF as possible (Figure 7b).
serial clock cycle and no conversion takes place (Figure 9). In all power-down modes, the interface remains active with the conversion results available at DOUT. Additionally, the input overvoltage protection remains active in all power-down modes (MAX1272). The first high bit on DIN after CS falls (start condition) powers up the MAX1272/MAX1273 from any softwareselected power-down condition. With external reference mode, device power-up time from full powerdown is typically 10s. Send a control byte and allow 10s for the device to wake up from full power-down. The next received control byte initiates a conversion. When in internal reference mode, full power-down mode disables the internal reference and reference buffer. Only the interface circuitry remains active for reading conversion results. Send a control byte and allow 2ms (CREF = 1F) for the internal reference to settle and the MAX1272/MAX1273 to wake up from full power-down mode. The next received control byte initiates a conversion.
Power-Down Modes
To save power, configure the ADC for a low-current shutdown mode by setting the PD bit in the control byte. The MAX1272/MAX1273 features four programmable power-down modes: delayed standby powerdown, immediate standby power-down, delayed full power-down, and immediate full power-down. Select standby or full power-down by programming MODE1 in the input control byte (Table 4). Select delayed or immediate power-down by programming MODE0 in the input control byte. Use the MODE0 bit to choose when the part enters the power-down state. For example, when MODE0 of the control byte is 0, the device remains powered up until after the current conversion ends (Figure 8). On the other hand, if MODE0 = 1, the device powers down on the falling edge of the eighth
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
AutoShutdownTM
The MAX1272/MAX1273 automatically enter standby power-down mode after each conversion without requiring any startup time on the next conversion.
Digital Interface
The MAX1272/MAX1273 feature a fully compatible SPI/QSPI and MICROWIRE serial interface. For SPI and QSPI, clear CPOL and CPHA in the microcontroller's SPI control registers.
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13
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
CS
RESERVED
RNG
RNG
REF
HI-Z
MSB
LSB
REF
BIP
BIP
PD
DIN
START
MODE1
MODE0
RESERVED
0
MODE1
START
0
HI-Z
D11
D10
D8
D9
D4
D5
D2
D1
D7
D6
16
D3
D0
DOUT
24
SCLK
ACQUISITION 4 SCLKs POWERED UP
CONVERSION 12 SCLKs POWERED UP POWERED DOWN
Figure 8. Delayed Power-Down Timing
CS
RESERVED
RNG
RNG
REF
BIP
HI-Z DOUT
REF
BIP
PD
DIN
MODE1
RESERVED
MODE1
START
MODE0
START
0
1
HI-Z
16
SCLK
ACQUISITION 4 SCLKs POWERED UP POWERED DOWN POWERED UP
Figure 9. Immediate Power-Down Timing
SPI and MICROWIRE Interface
When using the SPI (Figure 10a) or MICROWIRE (Figure 10b) interfaces, set CPOL = 0 and CPHA = 0 in the SPI master. Conversion begins with a falling edge on CS. Three consecutive 8-bit readings are necessary to obtain the entire 12-bit result from the ADC. DOUT data transitions on the serial clock's falling edge. The first 814
bit data stream contains all leading zeros. The second 8-bit data stream contains a leading zero followed by the MSB through D5. The third 8-bit data stream contains D4-D0 followed by trailing zeros.
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24
32
1
8
32
1
8
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and CPHA = 0, the MAX1272/MAX1273 support a maximum fSCLK of 1.4MHz. Figure 11 shows the MAX1272/ MAX1273 connected to a QSPI master. C on SCLK's rising edge. The first 8-bit data stream contains all zeros. The second 8-bit data stream contains a leading zero followed by the MSB through D5. The third 8-bit data stream contains bits D4-D0 followed by trailing zeros.
MAX1272/MAX1273
PIC16 with SSP Module and PIC17 Interface
The MAX1272/MAX1273 are compatible with a PIC16/PIC17 controller (C) using the synchronous serial-port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 12 and configure the PIC16/PIC17 as system master by initializing its synchronous serialport control register (SSPCON) and synchronous serialport status register (SSPSTAT) to the bit patterns shown in Tables 5 and 6. In SPI mode, the PIC16/PIC17 Cs allow 8 bits of data to be transmitted and received simultaneously. Three consecutive 8-bit readings are necessary to obtain the entire 12-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the
Transfer Function
Output data coding for the MAX1272/MAX1273 is binary in unipolar mode with: FS 1LSB = 4096 and two's complement binary in bipolar mode with: 2 x | FS | 1LSB = 4096 Code transitions occur halfway between successive integer LSB values. Figures 13a and 13b show the input/output transfer functions for uni-polar and bipolar operations, respectively. For full-scale (FS) values, see Tables 2 and 3.
I/O SCK MISO SPI VDD
CS SCLK DOUT MICROWIRE
I/O SCK SI
CS SCLK DOUT
SS
MAX1272 MAX1273
MAX1272 MAX1273
Figure 10a. SPI Connections
Figure 10b. MICROWIRE Connections
VDD
VDD
CS SCK MISO QSPI VDD
CS SCLK DOUT
SCLK DOUT CS
SCK SDI I/O PIC16/PIC17
SS
MAX1272 MAX1273
MAX1272 MAX1273
GND
Figure 11. QSPI Connections
Figure 12. SPI Interface Connection for a PIC16/PIC17 15
______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
Table 5. Detailed SSPCON Register Contents--PIC16/PIC17
CONTROL BIT WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 X X 1 0 0 0 0 1 Synchronous Serial-Port Mode-Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16. SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write Collision Detection Bit Receive Overflow Detection Bit Synchronous Serial-Port Enable Bit: 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins. Clock Polarity Select Bit. CKP = 0 for SPI master mode section.
X = Don't care.
Table 6. Detailed SSPSTAT Register Contents--PIC16/PIC17
CONTROL BIT SMP CKE D/A P S R/W UA BF BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 1 X X X X X X SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT) SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer Full Status Bit
X = Don't care.
1 LSB = FS 4096 OUTPUT CODE (TWO'S COMPLEMENT) 0...111 0...110 0...101 0...100 1 LSB = 2FS 4096
OUTPUT CODE 1...111 1...110 1...101 1...100
0...001 0...000 1...111
0...011 0...010 0...001 0...000 01 2 3 4092 INPUT VOLTAGE (LSB) 4094 FS
1...011 1...010 1...001 1...000 -2048 -2046
-1 0 +1 INPUT VOLTAGE (LSB)
+2045 +2047
Figure 13a. Unipolar Transfer Function 16
Figure 13b. Bipolar Transfer Function
______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one star point (Figure 14), connecting the two ground systems (analog and digital). For lowest-noise operation, ensure that the ground return to the star ground's power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) can degrade the performance of the ADC's fast comparator. Bypass VDD to the star ground with a 0.1F capacitor located as close as possible to the MAX1272/ MAX1273's power-supply input. Minimize capacitor lead length for best supply-noise rejection. Add an attenuation resistor (5) to extremely noisy power supplies. The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC's resolution (N-bits): SNR = (6.02 N + 1.76) dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals: SINAD (dB) = 20 log [SignalRMS / (Noise + Distortion)RMS]
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1272/MAX1273 are measured using the endpoint method.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + V5 THD = 20 x log V1
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step-width and the ideal value of 1 LSB. A DNL error specification of 1 LSB guarantees no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in the time between samples. Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when the actual sample is taken.
where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest frequency component, excluding DC offset.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error).
______________________________________________________________________________________
17
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
Typical Operating Circuit
5V
SUPPLIES
0.1F
5V
VLOGIC = 5V
GND
VDD AIN
R* = 5 0.1F
CS SCLK
I/O SCK MOSI MISO P
MAX1272 MAX1273
GND 5V DGND
REF 1.0F GND
DIN DOUT
VDD
MAX1272 MAX1273
DIGITAL CIRCUITRY
*OPTIONAL
Figure 14. Power-Supply Grounding Connections
Chip Information
TRANSISTOR COUNT: 6146 PROCESS: BiCMOS
18
______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1272/MAX1273
______________________________________________________________________________________
PDIPN.EPS
19
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range MAX1272/MAX1273
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
4X S
8
8
INCHES DIM A A1 A2 b MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1
E
H
0.60.1
c D e E H L
1
1
0.60.1
S
D
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
c e b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
1 1
J
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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